Chapter 8 · Book pp. 119–126
Applied Digital Circuits 2: the Counter IC
เรียน-เล่น-รู้ กับวงจรดิจิทัลขั้นประยุกต์ 2 - ไอซีวงจรนับ
A counter circuit counts pulses or events coming into it. It usually works in binary and shows the result as binary, or in another form such as decimal or hexadecimal, depending on the design.
8.1 Binary counters วงจรนับเลขฐานสอง
A binary counter is a basic digital circuit with three main parts:
- Flip-flops — the core. Each stores the state of one bit. Common types are the D flip-flop and the JK flip-flop.
- A clock signal — makes the counter change state at set times.
- Logic gates — control the counter and set conditions, such as resetting or changing state.
There are four basic types of counter:
| Type | What it does | Example |
|---|---|---|
| Up counter | Counts upwards | 0 → 1 → 2 → 3 |
| Down counter | Counts downwards | 3 → 2 → 1 → 0 |
| Up-down counter | Can count up or down | — |
| Modulo counter | Has a set end value, then starts again | Modulo 4: 0 → 1 → 2 → 3 → 0 (or 0 → 3 → 2 → 1 → 0 counting down) |
Counters are used in timers, rev counters (tachometers), clock and timer circuits, waveform generators — and they are a foundation of digital systems and microcontrollers.
8.2 Starting with the JK flip-flop JK ฟลิปฟลอป
A flip-flop is a digital circuit with two outputs that are always opposite. The key to a counter is the T (toggle) flip-flop, made from a JK flip-flop.
The JK flip-flop grew from the RS flip-flop, which uses two NOR gates. A “1” on S sets it; a “1” on R resets it. But if R and S are both “1”, the state cannot be decided — so it was improved into the JK flip-flop.
The JK flip-flop fixes the problem: when both inputs are “1”, it toggles. So it can be used as a T flip-flop, the basic building block of a binary counter.
8.3 How digital counters work แนวทางการทำงานของวงจรนับ
8.3.1 Asynchronous counters
Join JK flip-flops wired as T flip-flops and you get a binary counter (Fig 8-3). In this 4-bit asynchronous counter, each flip-flop is clocked by the output of the one before. The first flip-flop’s output is the LSB. Four flip-flops count 16 states: 0–15 in decimal, 0000–1111 in binary, 0–F in hexadecimal.
It is simple, but each flip-flop waits for the one before, so the delays add up. If each takes 50 ns, four take 4 × 50 = 200 ns, so the highest frequency is 1 ÷ (200 × 10⁻⁹) = 5 MHz.
8.3.2 Synchronous counters
In a synchronous counter (Fig 8-4, 3 bits) the clock goes to every flip-flop at once, so they all change together.
- Pulse 1: FF1 changes from “0” to “1” → 001.
- Pulse 2: FF1 goes back to “0”, but Q1 was “1” just before, so FF2 changes and Q2 becomes “1” → 010.
- Pulse 3: FF1 changes → 011.
- Pulse 4: FF3 changes, because A2’s output, FF1 and FF2 were all “1” → 100. And so on up to 111, then back to 000 (Fig 8-5).
There is no build-up of delay, so it works at higher frequencies — but the circuit is more complex.
8.4 Controlling the count การควบคุมการนับ
A 4-bit counter normally counts 0000 to 1111 (0 to F). To make it stop at 9 (1001) — a decimal or BCD counter — check bits 2¹ (B) and 2³ (D). When the counter reaches ten, the binary is 1010, so B and D are both “1”. AND them together and send the result to every flip-flop’s reset. Now the circuit counts only 0 to 9.
8.5 The 74HC93 counter IC ไอซีวงจรนับ 74HC93
Designers usually use a counter IC rather than flip-flops and gates, because it needs far fewer parts. There are many: decimal counters and 4-bit binary counters, counting up or down. This chapter uses the 74HC93, a 4-bit asynchronous binary counter that is easy to use.
| Pin | Name | Job |
|---|---|---|
| 14 | CP0 | Clock input; counts on the falling edge of the clock |
| 1 | CP1 | Clock input for the second stage — connect it to QA |
| 2, 3 | MR1, MR2 | Master reset (see the table below) |
| 4, 6, 7, 13 | NC | No connection |
| 5 | Vcc | Supply, 2 to 6 V |
| 10 | GND | Ground |
| 12 | QA (Q0) | Output bit 0 — the LSB |
| 9 | QB (Q1) | Output bit 1 |
| 8 | QC (Q2) | Output bit 2 |
| 11 | QD (Q3) | Output bit 3 — the MSB |
| MR1 | MR2 | QD QC QB QA |
|---|---|---|
| 1 | 1 | 0 0 0 0 (reset) |
| 1 | 0 | Counts |
| 0 | 1 | |
| 0 | 0 |
The IC counts unless MR1 and MR2 are both “1”. When they are, it stops and QA–QD all read “0”.
Basic connections
- Connect MR1 (pin 2) and MR2 (pin 3) to ground.
- Connect Vcc (pin 5) to a 2–6 V supply.
- Connect GND (pin 10) to ground.
- Connect CP1 (pin 1) to QA / Q0 (pin 12).
- Feed the clock into CP0 (pin 14).
- Watch the outputs QA (pin 12), QB (pin 9), QC (pin 8) and QD (pin 11).
8.6 Testing the 74HC93 ทดลองใช้งานไอซีวงจรนับ 74HC93
In Fig 8-8, pushbutton S1 makes the clock pulses for CP0 (pin 14). The IC counts on every falling edge, and the count shows on four LEDs: QA is the LSB and QD the MSB. Each press adds one, up to 1111 (15) with all four LEDs on; the next pulse goes back to 0. It keeps going until the power is removed or MR1 and MR2 are both “1”.
🛠️ Lab 8.1 · Count with the 74HC93
- Build the circuit in Tinkercad (Fig 8-9).
- Click switch S1 and watch the four LEDs.
- Build it with real parts (Fig 8-10) and repeat step 2.
- You may find one press sometimes adds more than one. That is switch bounce: the contacts make the clock signal several times — too fast for you to see, but the IC counts them all. The fix is to put a 1–10 µF capacitor across S1 to remove the noise. This is called debouncing.
Key ideas
| Idea | Remember |
|---|---|
| RS flip-flop | S sets, R resets; R = S = 1 is not allowed |
| JK flip-flop | J = K = 1 toggles → T flip-flop |
| Asynchronous counter | Simple; delays add up (4 × 50 ns → 5 MHz max) |
| Synchronous counter | Shared clock, faster, more complex |
| BCD counter | Reset at 1010 using B AND D → counts 0–9 |
| 74HC93 | 4-bit async counter; CP1 to QA; MR1 = MR2 = 1 resets |
| Switch bounce | Debounce with 1–10 µF across the switch |
🛠️ Activity · Extend the counter
- In Tinkercad, press S1 eight times. Write the LED pattern after each press as binary and decimal.
- Add a 10 µF capacitor across S1 and check that each press now adds exactly one.
- Make it a BCD counter: connect QB (pin 9) to MR1 (pin 2) and QD (pin 11) to MR2 (pin 3) instead of grounding them. Does it now count 0–9?
- Replace S1 with the 555 astable from Chapter 5 (Project 7) as the clock. What happens?
Check yourself
Chapter 8 has worked explanations but no exercises, so these questions are my own, based on its pages.